In electronic or optical telecommunications, particularly wireless, the received signal is generally different than the transmitted signal due to distortion introduced by the transmission channel. The receiver can ideally retrieve the original transmitted signal by estimating the channel and then applying the estimate to the received signal. It follows that accurate channel estimation plays key role in successful data reception.
The power level of the received signal depends on the power used to transmit that same signal and the distance it traversed over the communication channel, and the received power can vary greatly from the transmitted power. For a MIMO receiver with multiple receive antennas which is becoming increasingly common, the signal received at different MIMO antennas may be received with different power levels. The receiver must be able to operate across the full signal range of course, which brings an added challenge to receiver design. This challenge continues in wireless radio access technologies still in the development stage such as 5G cellular high data rate transmissions.
When implementing a signal processing algorithm in a receiver, one part of the design work is to choose suitable lengths of digital words that are used internally within the receiver for the algorithm's calculations. Word lengths are generally chosen so that the complete calculation chain as a whole fulfils the performance requirements the receiver needs to meet for a given radio access technology. But it is desirable to minimize the word lengths to achieve minimum hardware costs. Throughout the receiver processing chain some sub-blocks will be more sensitive to the signal power level than others, and this sensitivity is at least in part built into the hardware due to the word length limits imposed when designing the receiver. For example, a receiver designed for a maximum word length of N bits typically will have its buffers (hardware) able to hold no more than N bits at once, so if a FFT operation needs to operate on N+7 bits to meet the minimum performance requirements due to the signal power being very low it may simply not be possible due to hardware constraints in the receiver.
Since the hardware calculation blocks in a receiver are designed to meet the performance requirements under the assumption of a specified range of signal power, that same receiver can be expected to perform relatively poorly when the signal level is significantly lower. This is because intermediate results from the power-sensitive sub-blocks become too inaccurate and these inaccuracies propagate through the remainder of the receiver processing chain. In short, the data reception processing may work well for a certain signal level but the receiver's performance often drops dramatically when the received signal level turns low. Embodiments of these teachings address this issue from the pelipective of the receiver design.